1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming isolation structures, such as trench isolation structures, for semiconductor devices by performing a dry chemical removal process.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element used in manufacturing such integrated circuit devices. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises doped source and drain regions that are formed in a semiconducting substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
To make an integrated circuit on a semiconducting substrate, the various semiconductor devices, e.g., transistors, capacitors, etc., are electrically isolated from one another by so-called isolation structures. Currently, most sophisticated integrated circuit devices employ so-called shallow trench isolation (STI) structures. As the name implies, STI structures are made by forming a relatively shallow trench in the substrate and thereafter filling the trench with an insulating material, such as silicon dioxide.
FIGS. 1A-1G depict one illustrative prior art process flow for forming an isolation structure for a device 10 that involves performing a wet etching or deglaze process. FIG. 1A depicts the device 10 at the point of fabrication where an illustrative screen or pad oxide layer 14 and an illustrative pad nitride layer 16 have been formed above the substrate 11. Also depicted in FIG. 1A is a patterned etch mask layer 18, e.g., a patterned photoresist mask, that may be formed using traditional photolithography tools and techniques. Thereafter, as shown in FIG. 1B, one or more etching processes are performed, such as reactive ion etching processes, through the etch mask layer 18 to pattern the pad nitride layer 16, the pad oxide layer 14 and to form a trench 20 in the substrate 11. The dimensions of the trench 20 may vary depending on the particular application. In current day devices, the trench 20 may have a depth of about 100-500 nm and a width (at the top) of about 30-100 nm. Next, as shown in FIG. 1C, an insulating material 22, such as silicon dioxide, an HDP oxide, a HARP oxide, a flowable oxide material, etc., is formed across the device 10 so as to over-fill the trench 20. Then, as shown in FIG. 1D, one or more chemical mechanical polishing (CMP) processes are performed on the device 10 to remove the portions of the layer of insulating material 22 positioned above the surface 16U of the pad nitride layer 16. This results in the formation of the isolation structure 22A. Thereafter, as shown in FIG. 1E, a wet etching or deglazing process (using, for example, a hot phosphoric acid solution) is performed to insure that the surface 16U of the pad nitride layer 16 is free of any remnants of the layer of insulating material 22. This deglaze process reduces the thickness of the isolation structure 22A, as reflected by the recessed upper surface 22U of the isolation structure 22A, e.g., the deglaze process reduces the thickness of the overall height or thickness of the isolation structure 22A by about 10-80 nm. Then, as shown in FIG. 1F, a wet etching process, i.e., a wet nitride strip process, is performed to remove the pad nitride layer 16. In some cases, an additional etching process, such as a dilute HF etching process, may be performed to remove the pad oxide layer 14, or the pad oxide layer 14 may be left in place or removed at a later point during the fabrication of the device 10. Using the illustrative technique depicted in FIGS. 1A-1F, the step height 22S, i.e., the distance between the upper surface 22U of the isolation structure 22A and the upper surface 11S of the substrate 11 may be about 15-30 nm.
FIGS. 2A-2C depict another illustrative prior art process flow for forming an isolation structure 22A for the device 10 that involves performing a dry deglaze process. FIG. 2A depicts the device 10 at a point of fabrication that corresponds to that depicted in FIG. 1E, i.e., after one or more CMP processes have been performed to remove the portions of the layer of insulating material 22 positioned above the surface 16U of the pad nitride layer 16. Next, as shown in FIG. 2B, a timed, dry, non-selective reactive ion etching (RIE) process is performed to remove portions of the silicon nitride layer 16 and portions of the isolation structure 22A. This dry etching process involves use of etchants that are capable of etching the underlying silicon substrate so the duration of the dry etching process must be controlled so as to avoid such an occurrence, i.e., the etching process must be stopped before the substrate 11 is reached. Accordingly, after the dry etching process is performed, there is typically a very thin layer of the pad nitride layer 16 remaining, e.g., 10-50 nm, as shown in FIG. 2B. Then, as shown in FIG. 2C, a wet etching process, i.e., a wet nitride strip process, is performed to remove the remaining portions of the pad nitride layer 16. As with the earlier method, in some cases, an additional etching process, such as a dilute HF etching process, may be performed to remove the pad oxide layer 14, or the pad oxide layer 14 may be left in place or removed at a later point during the fabrication of the device 10. Using the illustrative technique depicted in FIGS. 2A-2C, the step height 22S of the final isolation structure 22A may also be about 15-30 nm.
Numerous processing operations are performed in a very detailed sequence, or process flow, to form integrated circuit devices, e.g., deposition processes, etching processes, heating processes, masking operations, etc. One problem that arises with current processing techniques is that, after the STI regions are formed, at least portions of the STI regions are exposed to many subsequent etching or cleaning processes that tend to consume, at least to some degree, portions of the STI structures subjected to such etching processes. As a result, the STI structures may not perform their isolation function as intended, which may result in problems such as increased leakage currents, etc. Furthermore, since the erosion of the STI structures is not uniform across a die or a wafer, such STI structures may have differing heights, which can lead to problems in subsequent processing operations. For example, such height differences may lead to uneven surfaces on subsequently deposited layers of material, which may require additional polishing time in an attempt to planarize the surface of such layers. Such additional polishing may lead to the formation of additional particle defects, which may reduce device yields.
The present disclosure is directed to various methods of forming isolation structures that may eliminate or at least reduce one or more of the problems identified above.